Two types of data latches are commonly used in digital data processing systems. In a "transparent" latch, the output follows the corresponding input signal while the latch is enabled. When the enable signal is removed, the data then presented at the input terminal is latched, and the output terminal remains in such state regardless of further transitions at the input terminal until the latch is again enabled.
Another common latching circuit is an edge-triggered latch, also commonly known as a D-type flip-flop. In an edge-triggered latch, data at the input terminal is clocked to the output terminal on successive transitions, usually the falling edge, of a clock or strobe signal.
It is a common situation in many digital processing systems for data signals to be unstable for some initial period of time following the leading edge of a data strobe. If the data strobe is used as the enable signal for a transparent latch, the output signal will be initially unstable since the output signal follows the input signal. As long as the data is valid at the falling edge of the data strobe, a transparent latch will retain valid data. An edge triggered latch using the falling edge of the data strobe will always capture valid data and will be free of transients caused by the initial instability of the input signal. However, valid data from such an edge-triggered latch is not available until the falling edge of the data strobe, and this may not be acceptable to meet timing constraints of the system. In such situations, use of a transparent latch is advantageous since valid output data is available sooner.
In some applications, it is desirable to qualify a transparent latch with a clock signal which acts as an additional enable signal. Thus, the latch is enabled only when both the enable signal and the clock signal are high. With this arrangement, valid data is unavailable before the leading edge of the clock signal, and again this may be inconsistent with timing constraints of the system.